CONCURRENT ERROR-DETECTION IN FAST FERMAT NUMBER TRANSFORM NETWORKS

For many real-time and scientific applications, it is desirable to per form signal and image processing algorithms by means of special hardwa re at very high speed. With the advent of VLSI technology, large colle ctions of processing elements can be used to achieve high-speed comput ations. In such designs, some level of fault tolerance must be obtaine d to ensure the validity of the results. Fermat number transforms (FNT s) are attractive for the implementation of digital convolution becaus e the computations are carried out in modular arithmetic which offers three advantages: no roundoff error, no multiplications in the transfo rm, and decomposition into fast algorithm analogous to the FFT. In thi s paper we present a fault detectable array architecture for the fast implementation of Fermat number transform. The results show that the d esign offer concurrent error detection (CED) using very low hardware a nd time overheads.