Algorithms to select IDDQ measurement vectors for bridging faults in sequential circuits

In order to reduce IDDQ testing time, it is important to reduce the number of IDDQ measurement vectors, because IDDQ measurement is a time-consuming p rocess. For obtaining minimum number of IDDQ measurement vectors for sequen tial circuits, fault simulation needs to be performed without fault-droppin g, thus requiring very high simulation time. In this paper we propose algor ithms to select small number of IDDQ measurement vectors. The proposed algo rithms can concurrently simulate multiple faults and use heuristics for sel ection of IDDQ measurement vectors to reduce simulation time. Experimental results are presented to demonstrate the effectiveness of the proposed meth od.