I-DDQ testing of submicron CMOS-by cooling ?

Authors
Rencz, M Szekely, V Torok, S Torki, K Courtois, B
Citation
M. Rencz et al., I-DDQ testing of submicron CMOS-by cooling ?, J ELEC TEST, 16(5), 2000, pp. 453-461
Citations number
14
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
ISSN journal
09238174 → ACNP
Volume
16
Issue
5
Year of publication
2000
Pages
453 - 461
Database
ISI
SICI code
0923-8174(200010)16:5<453:ITOSCC>2.0.ZU;2-A
Abstract
The usability of I-DDQ testing is limited by the subthreshold currents of t he low-V-T, submicron MOS transistors in the low bias voltage circuits. The paper addresses the cooling of the chip in order to overcome this problem. Experimental results concerning the effect of cooling on the threshold vol tage and subthreshold current are presented in the range of -75 ... 25 Cent igrade. The subthreshold currents decrease by a factor of about 100-1000 by cooling-down the chip to -75 Centigrade.