Testing the local interconnect resources of SRAM-Based FPGA's

This paper addresses the problem of testing the configurable modules used i n the local interconnect of SRAM-based FPGAs. First, it is demonstrated tha t a n address bit Configurable Interface Multiplexer requires N = 2(n) test configurations considering a stuck-at as well as a functional fault model. Second, a logic cell with a set of k input Configurable Interface Modules with n address bits is analyzed and it is proven that the set of CIMs can b e tested in parallel making the number of required test configurations equa l to N = 2(n). Third, it is shown that the complete circuit i.e. a m x m ar ray of sets of k Configurable Interface Multiplexers with n address bits ca n be tested with only N = 2(n) test configurations using the XOR tree and s hift register structures.