Hardware/software co-design of run-time schedulers for real-time systems

We present the SERRA Run-Time Scheduler Synthesis and Analysis Tool which a utomatically generates a run-time scheduler from a heterogeneous system-lev el specification in both Verilog HDL and C. Part of the run-time scheduler is implemented in hardware, which allows the scheduler to be predictable in being able to meet hard real-time constraints, while part is implemented i n software, thus supporting features typical of software schedulers. SERRA's real-time analysis generates a priority assignment for the software tasks in the mixed hardware-software system. The tasks in hardware and sof tware have precedence constraints, resource constraints, relative timing co nstraints, and a rate constraint. A heuristic scheduling algorithm assigns the static priorities such that a hard real-time rate constraint can be pre dictably met. SERRA supports the specification of critical regions in softw are, thus providing the same functionality as semaphores. We describe the task control /data-flow extraction, synthesis of the contro l portion of the run-time scheduler in hardware, real-time analysis and pri ority scheduler template. We also show how our approach fits into an overal l tool flow and target architecture. Finally, we conclude with a sample app lication of the novel run-time scheduler synthesis and analysis tool to a r obotics design example.