A morphological filter chip using a modified decoding function

This paper proposes a new very large scale integration architecture for cos t-effective morphological filters and presents its design and chip implemen tation. The proposed architecture can reduce the hardware cost by using a f eedback loop path and a decoder/encoder pair comparator. The feedback loop path can reuse partial results to reduce the number of add/subtract units. The decoder/encoder pair comparator using a modified decoding function can reduce the gate count and propagation delay especially when the size of mor phological operations increases. We used the 0.8-mu m SOG cell library (KG6 0K) and the total number of gates is only 2667. The proposed morphological filter chip has actually been fabricated and is running at 30 MHz that meet s the real-time image processing requirement of the ITU-R BT.601 standard.