A new CMOS buffer without short-circuit power consumption is proposed. The
gate- driving signal of the output pull-up (pull-down) transistor is fed ba
ck to the output pull-down (pull-up) transistor to get tri-state output mom
entarily, eliminating the short-circuit power consumption. The HSPICE simul
ation results verified the operation of the proposed buffer and showed the
power-delay product is about 15% smaller than conventional tapered CMOS buf
fer.