A CMOS buffer without short-circuit power consumption

Authors
Yoo, C
Citation
C. Yoo, A CMOS buffer without short-circuit power consumption, IEEE CIR-II, 47(9), 2000, pp. 935-937
Citations number
4
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
ISSN journal
10577130 → ACNP
Volume
47
Issue
9
Year of publication
2000
Pages
935 - 937
Database
ISI
SICI code
1057-7130(200009)47:9<935:ACBWSP>2.0.ZU;2-4
Abstract
A new CMOS buffer without short-circuit power consumption is proposed. The gate- driving signal of the output pull-up (pull-down) transistor is fed ba ck to the output pull-down (pull-up) transistor to get tri-state output mom entarily, eliminating the short-circuit power consumption. The HSPICE simul ation results verified the operation of the proposed buffer and showed the power-delay product is about 15% smaller than conventional tapered CMOS buf fer.