A CMOS pulse-shrinking delay element for time interval measurement

A deep sub-nanosecond resolved CMOS pulse-shrinking delay element used in t he time-to-digital converter (TDC) is proposed. The pulse-shrinking capabil ity of the element is controlled by the dimension ratio of the adjacent gat es. This control mechanism is completely different from the bias adjustment adopted in the conventional pulse-shrinking element. Without the need of c ontinuous calibration, the presented element possesses not only extremely f ine resolution, small single-shot errors, low power consumption, but also g ood insensitivity to the supply voltage variation. Being fabricated with 0. 35-mu m CMOS technologies, the TDC made of the new elements has been measur ed to have a resolution of 68 ps. The effective resolution only varies 1.5 ps for a rather large supply voltage range from 3.5 to 4.5 V. The size of t he circuit is 0.35 mm x 0.09 mm only, excluding the I/O pads. Under a singl e 3.3-V power supply, the static power dissipation, including the I/O pads, is 1 mu W. The average power consumption is measured to he merely 1.2 mW u nder a measurement rate of 100 ksps.