Parametric compact models for flip chip assemblies

A parametric thermal compact modeling study of flip chip assemblies is pres ented. First, a star network of four thermal resistors was found to be opti mal for a flip chip with arbitrary geometry and material properties. In a s econd step several parameters such as thermal underfill conductivity and di e size were varied. The effect of these variations on the values of the fou r thermal resistors of the compact model is Investigated. In a third step, a response surface model is derived from these compact models, which gives end-users the possibility to choose a flip chip with arbitrary geometry and deduce automatically the corresponding thermal compact model, Having the c ompact model, it is now possible to apply customer specific boundary condit ions to this compact model and compute the maximal temperature reached at t he junction of the flip chip assembly in the specified environment.