Exploiting parallelism in geometry processing with general purpose processors and floating-point SIMD instructions

Three-dimensional (3D) graphics applications have become very important wor kloads running on today's computer systems. A cost-effective graphics solut ion is to perform geometry processing of 3D graphics on the host CPU and ha ve specialized hardware handle the rendering task. In this paper, we analyz e microarchitecture and SIMD instruction set enhancements to a RISC supersc alar processor for exploiting parallelism in geometry processing for 3D com puter graphics. Our results show that 3D geometry processing has inherent p arallelism. Adding SIMD operations improves performance from 8 percent to 2 8 percent on a 4-issue dynamically scheduled processor that can issue at mo st two floating-point operations. In comparison, an 8-issue processor, igno ring cycle time effects, can achieve 20 to 60 percent performance improveme nt over a 4-issue. If processor cycle time scales with the number of ports to the register file, then doubling only the floating-point issue width of a 4-issue processor with SIMD instructions gives the best performance among the architectural configurations that we examine (the most aggressive conf iguration is an 8-issue processor with SIMD instructions).