A fabrication process for integrating polysilicon microstructures with post-processed CMOS circuits

A MEMS-first fabrication process for integrating CMOS circuits with polysil icon micromechanical structures is described in detail. The overall process uses 18 masks (22 lithography steps) to merge a p-well LOGOS CMOS process that has one metal and two polysilicon layers with a surface micromachining process that has three layers of polysilicon. The microstructures are form ed within recesses on the surface of silicon wafers such that their uppermo st surfaces are coplanar with the remainder of the substrate. No special pl anarization technique, such as chemical-mechanical polishing, is used in di e work described here. Special aspects of the process include provisions to improve lithography within the recesses, to protect the microstructures du ring the circuit fabrication, and to implement an effective lead transfer b etween the microstructures and the on-chip circuitry. The process is valida ted using a test vehicle that includes accelerometers and gyroscopes interf aced with sensing circuits. Measured transistor parameters match those obta ined in standard CMOS, with NMOS and PMOS thresholds at 0.76 V and -0.96 V, respectively.