A modular multi-chip neuromorphic architecture for real-time visual motionprocessing

The extent of pixel-parallel focal plane image processing is limited by pix el area and imager fill factor. In this paper, we describe a novel multi-ch ip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in th e focal plane. This multi-chip system retains the primary advantages of foc al plane neuromorphic image processors: low-power consumption, continuous-t ime operation, and small size. The two basic VLSI building blocks are a pho tosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two- chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing system s are described. The first three-chip system uses two sender chips to compu te the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resultin g in information about image translation, rotation, and expansion. These th ree-chip systems demonstrate the modularity and flexibility of the multi-ch ip neuromorphic approach.