Challenges for atomic scale modeling in alternative gate stack engineering

Citation
A. Kawamoto et al., Challenges for atomic scale modeling in alternative gate stack engineering, IEEE DEVICE, 47(10), 2000, pp. 1787-1794
Citations number
41
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
47
Issue
10
Year of publication
2000
Pages
1787 - 1794
Database
ISI
SICI code
0018-9383(200010)47:10<1787:CFASMI>2.0.ZU;2-N
Abstract
We review the challenges for atomic scale modeling of alternative gate diel ectric stacks. We begin by highlighting recent achievements of state-of-the -art atomistic simulations of the Si/SiO2 system, showing how such calculat ions have elucidated the microscopic origins of several important experimen tal phenomena. For the benefit of readers who may be unfamiliar with the si mulation tools, we overview and compare the relevant methods, We then descr ibe the difficulties encountered in extending these approaches to investiga te high-kappa dielectric stacks, pointing out exciting research directions aimed at overcoming these challenges. We conclude by presenting a roadmap o f computational goals for atomic scale modeling of alternative gate dielect rics.