Application of silicon-based process simulation tools to the fabrication of heterojunction bipolar transistors

Process simulation is not widely used to date in the compound semiconductor industry. This is due in part to several issues that exist in applying com mercially available simulation tools that were designed for silicon integra ted circuits (ICs), to the fabrication of III-V-based devices. These issues arise from the inherent differences in the fabrication techniques used in the separate device technologies. Computer simulations have been applied to model heterojunction bipolar transistor (HBT) fabrication at HRL Laborator ies, LLC, These silicon-based simulations require calibration to accurately model the profiles produced during III-V device and IC fabrication. The ca libration method includes the production of simulated cross sections, which are then compared with focused ion beam cross sections of actual devices.