FPGA based front-end electronics for a high resolution PET scanner

A high resolution PET scanner requiring processing electronics for 936 bloc k technology channels and just under sixty-thousand crystal elements has be en developed. With the advances in flexibility, number of gates, lower cost s and speed of Field Programmable Gate Arrays (FPGA), an FPGA implementatio n of the front-end processing electronics was chosen over the traditional d iscrete logic or Application Specific Integrated Circuit (ASIC) [1]. The FP GA architecture reduced the development time and risks compared to a mask-b ased ASIC architecture while keeping costs and electronics packing density comparable. The extensive use FPGAs enables much faster circuit realization and a very efficient logic utilization by allowing re-configuration of the electronics functionality to support system setup, self-diagnostics, and s everal calibration modes for detector setup. Logic realized within the FPGA s performs the crystal selection, energy qualification, time correction, de pth of interaction determination, and event counting functions. Since the F PGAs are in-circuit re-configurable (ICR), the functionality of the electro nics is easily modified to support the different modes of operation. Thus t he development time is reduced as well as the amount of electronics require d, saving board area, power consumption and costs.