Improving memory traffic by assembly-level exploitation of reuses for vector registers

In this paper, we propose a compilation scheme to analyze and exploit the i mplicit reuses of vector register data. According to the reuse analysis, we present a translation strategy that translates the vectorized loops into a ssembly vector codes with exploitation of vector reuses. Experimental resul ts show that our compilation technique can improve the execution time and t raffic between shared memory and vector registers. Techniques discussed her e are simple, systematic, and easy to be implemented in the conventional ve ctor compilers or translators to enhance the data locality of vector regist ers.