Study of triggering inhomogeneities in gg-nMOS ESD protection devices via thermal mapping using backside laser interferometry.

Inhomogeneities in the parasitic bipolar transistor triggering during an el ectrostatic discharge (ESD) event are analyzed in 0.35 mu m technology grou nded-gate nMOSFET ESD protection devices operating in snapback. The current density during high current stress is studied by monitoring the temperatur e-induced increase in optical phase shift using a backside infrared laser i nterferometric technique. The distribution of the current along the gate wi dth and the triggered width are investigated as a function of the applied s tress current magnitude and device layout parameters. Below a critical stre ss current the parasitic bipolar transistor triggers inhomogeneously, first at the corners and then in the central part of the device. Under these con ditions the current density in the triggered region of the device is nearly constant. At stresses higher than the critical current the device is homog eneously triggered, exhibiting a linear increase of the current density wit h the stress current in the device. The experimental results are explained in terms of 3D layout effects and compared to results of 3D electrical devi ce simulation. (C) 2000 Elsevier Science Ltd. All rights reserved.