Numerical investigation for a Grounded Gate NMOS Transistor under electrostatic discharge (ESD) through TLP method

Authors
Galy, P Berland, V Foucher, B Lombaert-Valot, I Guilhaume, A Chante, JP Dufrenne, S Bardy, S
Citation
P. Galy et al., Numerical investigation for a Grounded Gate NMOS Transistor under electrostatic discharge (ESD) through TLP method, MICROEL REL, 40(8-10), 2000, pp. 1473-1477
Citations number
5
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
MICROELECTRONICS RELIABILITY
ISSN journal
00262714 → ACNP
Volume
40
Issue
8-10
Year of publication
2000
Pages
1473 - 1477
Database
ISI
SICI code
0026-2714(200008/10)40:8-10<1473:NIFAGG>2.0.ZU;2-R
Abstract
For many years,design of robust ESD cell becomes critical due to the ever i ncreasing density of technology process. This paper presents the main resul ts of a numerical investigation of a Grounded Gate NMOS Transistor (GGNMOST ) under Transmission Line Pulse (TLP). The simulation tool is the Davinci s oftware. It allows to calculate the TLP response curves of the device under test. Afterwards the numerical results and the experimental ones are compa red for assessment and simulation validation. (C) 2000 Elsevier Science Ltd . All rights reserved.