Stability of polysilicon thin film transistors under switch operating

Ageing of low temperature polysilicon Thin Film Transistors (TFTs) under AC gate bias stress is reported in this study. The active layer of these high performances transistors is amorphous deposited using Low Pressure Chemica l Vapor Deposition (LPCVD) technique. The drain and source regions are in-s itu doped during the LPCVD deposition by using phosphine to fabricate n-typ e transistors. The active layer and the drain and source regions are Solid Phase Crystallized. The field effect mobility is higher than 100 cm(2)/V.s, the subthreshold slope around 0.6 V/dec, the threshold voltage around 0.2V and the switching time around 370 nsec. As these TFTs are commonly used as switching devices in the most of applica tions in large area electronics field, the study of their stability under A C electrical stress is important. The present work shows that the effect of the positive or negative DC stress is higher than that of the AC stress an d then the degradation of polysilicon TFTs is over-estimated when it is che cked from the effects of DC gate bias stress Degradation under bias stress is shown to originate from the creation of ga p states at the channel-interface oxide and in the channel material. The lo wer influence of the AC stress is explained from an annealing effect of the created states by the application of an opposite sign bias stress. (C) Pub lished by Elsevier Science Ltd.