Overstress and electrostatic discharge in CMOS and BCD integrated circuits

The ESD qualification of the new technologies is obtained by testing differ ent device structures an comparing the ESD robustness evaluated by means of different testing methods (HBM, MM, CDM and TLP). The influence of the lay out parameters on the ESD robustness must also be characterized. In this pa per we will present data concerning the ESD robustness of both 0.35 mu m CM OS and 0.6 mu m smart power (BCD5) protection structures. A study of the in fluence of layout parameters on the ESD robustness with different test meth ods (HBM, CDM and TLP) will be given. Failure analysis by means of electric al characterization, Emission Microscopy and SEM inspection will also been presented. (C) 2000 Elsevier Science Ltd. All rights reserved.