THE I(2)C-BUS IN DISCRETE-TIME PROCESS ALGEBRA

Using discrete time process algebra with relative timing, a model for the (IC)-C-2-bus is designed. The model of the (IC)-C-2-bus is divided into three parts: a model for the bus lines, a model for the master i nterfaces and a model for the slave interfaces. The model of the bus l ines is based on a model for a wired-AND. For the models of the interf aces, the approach is to start from a high level bus protocol and refi ne it step by step. First, a single master without timing constraints is considered. Then the model is adapted to deal with the timing const raints. Then also the restriction to a single master is relaxed. It tu rns out that the model for the slave interfaces can be based on the mo del for the master interfaces. The use of the model obtained is discus sed and illustrated. (C) 1997 Published by Elsevier Science B.V.