Design of fast high-radix SRT dividers and their VLSI implementation

Division accounts for a significant fraction of the total arithmetic operat ions, and most implementations for the division are based on the SRT algori thm that uses a recurrence producing one quotient digit for each step. The complexity of the quotient-digit selection process can be simplified signif icantly by using a look-up table, referred to as the quotient-digit selecti on table (QST). However, the table size of the conventional QST approach in creases unmanageably as the radix increases. For fast high-radix applicatio ns, the study proposes an alternative approach which determines the quotien t digit using two much smaller tables instead of a huge table for the conve ntional approach. The proposed process is comprised of two major steps: est imation of quotient digit; and correction of the estimated quotient digit a nd updating the partial remainder. Results show that the table size is redu ced significantly. Further, an estimation limit is introduced to keep the t able size reasonably small when the radix increases. Thus the proposed appr oach can be well-suited for high-radix implementation.