Low power architecture for floating paint MAC fusion

With the proliferation of floating point computing applications, the demand for high performance, low power floating point hardware has increased. A n ew architecture for low power floating point multiply-accumulate fusion is presented. The proposed architecture minimises power consumption through tr ansition activity scaling and data path simplifications. The switching acti vity function of the proposed MAF is represented as a four-state FSM. Durin g any given operation cycle, only a limited set of functional subunits are active, during which time, the logic assertion status of the circuit nodes of the unused functional units are maintained at their previous states. Cri tical path delay and latency are reduced by incorporating data path simplif ications and speculative rounding. The scheme offers a worst case power red uction of more than 49%.