Evolutionary synthesis of fast constant-coefficient multipliers

This paper presents an efficient graph-based evolutionary optimization tech nique called Evolutionary Graph Generation (EGG), and its application to th e design of fast constant-coefficient multipliers using parallel counter-tr ee architecture. An important feature of EGG is its capability to handle th e general graph structure: directly in evolution process instead of encodin g the graph structures into indirect representations, such as bit strings a nd trees. This paper also addresses the major problem of EGG regarding the significant computation time required fur verifying the function of generat ed circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG syste m can create efficient multiplier structures which are comparable or superi or to the known conventional designs.