A 3.3 V power feedback chip for linearization of RF power amplifiers

The power feedback technique is a simple and low cost linearization scheme suitable for consumer products such as hand sets. This paper presents a cus tom chip for linearization of RF power amplifiers using power feedback. The chip, implemented in a standard double-metal double-poly 0.6 mu m CMOS pro cess, operates with 3.3 V supply voltage and consumes 62 mW. When it was us ed to linearize a commercially available high efficiency RF power amplifier at 850 MHz, experimental results showed that out-of-band power at 30 kHz o ffset was reduced some 10 dB for a pi/4-shifted DQPSK modulated North Ameri can digital cellular (NADC) signal. For the same level of adjacent channel interference (ACI), the efficiency was increased from 35% to 48%.