Low-power area-efficient pipelined A/D converter design using a single-ended amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/ D converter using a single-ended amplifier. The proposed multiply-by-two si ngle-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a s mall capacitor mismatch sensitivity, allowing us to use a smaller capacitan ce. The simple high-gain dynamic-biased regulated cascode amplifier also ha s an excellent switching response. These properties lead to the low-power a rea-efficient design of high-speed A/D converters. The estimated power diss ipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSampl e/s.