Differential analog data path DC offset calibration methods

DC offset causes performance degradation in signal processing systems espec ially for high-speed applications. A new offset cancellation method that re laxes the requirement for the offset of the circuit components in the diffe rential analog data path to about 10 times larger is introduced. This metho d moves the adjusting target from analog-to-digital converter (ADC) to its input buffer and adjusts DC level of ADC input to its center before the fin al offset cancellation. It eliminates post-production adjustment such as fu se trimming, which increases the cost and TAT in manufacturing and testing. Execution and simulation times are shortened down to 1/9 for less settling time in buffer and with improved logic. An automatic quick offset calibrat ion circuit is implemented in a small silicon space in a high-speed hard di sk drive (HDD) channel with 0.25-mu m four-layer metal CMOS process. The me asured data show this method works effectively in this system.