Layout dependent matching analysis of CMOS circuits

Layout has strong influence on matching properties of a circuit. Current ma tching models, which characterize both local random non-uniformities and gl obal systematic non-uniformities stochastically, are not adequate for the m atching analysis taking the effect of layout realization into account. In o rder to consider topological information of layout into matching analysis, we propose a matching model which treats the random and systematic componen ts separately. Also, we characterize the micro-loading effect, which modula tes fabricated line-width according to the local density of layout patterns , into matching analysis. With these two techniques, we can perform matchin g analysis of CMOS circuits taking layout information into account.