1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs

Multithreshold-voltage CMOS (MTCMOS) has a great advantage of lowering phys ical threshold voltages without increasing the power dissipation due to lar ge subthreshold leakage currents. This paper presents the embedded SRAM tec hniques for high-speed low-power MTCMOS/SIMOX application-specified integra ted circuits (ASICs) that are operated with a single battery cell of around I V, In order to increase SRAM operating frequency, a pseudo-two-stage pip eline architecture is proposed. The address decoder using a pass-transistor -type NAND gate and a segmented power switch presents a short clocked wordl ine selection time, The Large bitline delay in read operations is greatly s hortened with a new memory cell using extra low-V-t1, nMOSs, The small read out signal from memory cells is detected with a high-speed MTCMOS sense amp lifier, in which a pMOS bitline selector is merged. The wasted power dissip ation in writing data is reduced to zero with a self-timed writing action. A 8 K-words x 18-bits SRAM test chip, fabricated with a 0.35-mu m MTCMOS/SI MOX process (shortened effective channel length of 0.17 mu m is available), has demonstrated a 100-MHz operation under the worst power-supply conditio n of 1 V, At a typical 1.2 V,the power dissipation during the standby time is 0.2-mu W and that of a 100-MHz operation with a checkerboard test patter n is 14 mW for single fan-in loads.