A phase-locked loop (PLL) with a fast-locked discriminator-aided phase dete
ctor (DAPD) is presented. Compared with the conventional phase detector (PD
), the proposed fast-locked PD reduces the PLL pull-in time and enhances th
e switching speed, while maintaining better noise bandwidth. The synthesize
r has been implemented in a 0.35-mu m CMOS process, and the output phase no
ise is -99 dBc/Hz at 100-kHz offset. Under the supply voltage of 3.3 V, its
power consumption is 120 mW.