A 2-V 10.7-MHz CMOS limiting amplifier/RSSI

This paper presents low-voltage low-power CMOS circuit design techniques fo r an intermediate frequency (IF) limiting amplifier and received signal str ength indicator (RSSI), The architecture of the limiting amplifier and RSSI employed is determined by the optimal power consumption for a specified sp eed, overall gain, and accuracy. Each gain cell of the Limiting amplifier e mploys folded diode load for low-voltage operation. Offset is reduced by a cross-connected source-coupled pair offset subtractor that is along the sig nal path. Full-wave current rectification and summation are employed in the RSSI circuit to achieve high precision while maintaining low voltage and t on: power. Using a single 2-V supply voltage, measured results demonstrate the input dynamic range is larger than 75 dB for 10.7-MHz IF application. T he prototype occupies an active area of 0.4 mm(2) using a 0.6-mu m digital CMOS technology. The power dissipation is 6.2 mW.