Fault diagnosis technology using I-DDQ and linkage of diagnosed result to the wafer inspection data

Abnormal I-DDQ (quiescent V-DD supply current) indicates the existence of p hysical damage in a circuit. Using this phenomenon, a CAD-based fault diagn osis technology has been developed to analyze the manufacturing yield of lo gic LSI. This method to detect the fatal defect fragments in several abnorm alities identified with wafer inspection apparatus includes a way to separa te various leakage faults and to define the diagnosis area encircling the a bnormal portions. The diagnosis method progressively narrows the faulty are a by using logic simulation to extract the logic states of the diagnosis ar ea, and by locating test vectors related to abnormal I-DDQ. The fundamental diagnosis method employs the comparative operation of each circuit. The ob tained result is investigated to analyze the manufacturing process having t he greatest influence on yield and to classify the fault mode. This defect information is fed back to logic LSI manufacturing processes, helping to im prove manufacturing yield.