A digital CDR circuit for PON systems

This paper describes a digital CDR (Clock Data Recovery) circuit for PON (P assive Optical Network) systems. The performance of this CDR circuit shows 0.4U.I.p-p jitter and +/-40% duty cycle distortion tolerance within a 2bit pull-in time. The circuit has been implemented on a 3.3V, 0.35 mu m CMOS ce ll-based IC, and used for NEC's PON systems of 50Mbps similar to 156Mbps. W hen evaluated, the performance of this CDR circuit combined with an O/E con verter met the ITU-T G.983 standard (FSAN specification), and the power pen alty of the CDR circuit was found to be less than 0.1dB. Because a digital CDR circuit with a very low power penalty enables a PON system with a wide range of optical power levels, it will be valuable in the realization of an economical access network.