WARP REDUCTION OF HIGH-ELECTRON-MOBILITY-TRANSISTOR ON SI WAFER BY IN-DOPED SELECTIVELY DOPED HETEROSTRUCTURE AND STRAINED-LAYER SUPERLATTICE BUFFER LAYER

Structure to reduce warp of high electron mobility transistors (HEMT) on Si wafers is investigated. The proposed structure consists of an In -doped selectively doped heterostructure and a strained layer superlat tice buffer layer. Upon reducing the stress and the total epitaxial la yer thickness, the warp of our proposed HEMT structure grown on a 3-in ch-diameter Si wafer was reduced to about 1/3 of that of the conventio nal structures. Using the Fox-Jesser strain relaxation theory, we anal yzed the stress reduction mechanism. We found that the frictional forc e acting on dislocations is important for stress reduction of In-relat ed compounds. We fabricated HEMT ring oscillator circuits with gate le ngth of 0.4 mu m The circuits had a delay time of 19.1 ps/gate and pow er consumption of 0.175 mW/gate. These values are comparable with thos e on GaAs substrates.