Analytic model of parasitic capacitance attenuation in CMOS devices with hyper-thin oxides

Citation
K. Ahmed et al., Analytic model of parasitic capacitance attenuation in CMOS devices with hyper-thin oxides, ELECTR LETT, 36(20), 2000, pp. 1699-1700
Citations number
11
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
ELECTRONICS LETTERS
ISSN journal
00135194 → ACNP
Volume
36
Issue
20
Year of publication
2000
Pages
1699 - 1700
Database
ISI
SICI code
0013-5194(20000928)36:20<1699:AMOPCA>2.0.ZU;2-5
Abstract
The parasitic accumulation capacitance attenuation in MOS structures with h yper-thin oxides has been modelled using a distributed RC network. The simp le analytic model is in excellent agreement with a two-dimensional numerica l simulation and experimental data.