Integrating variable-latency components into high-level synthesis

This paper presents techniques to integrate the use of variable-latency uni ts in a high-level synthesis (HLS) design methodology. Components used as b uilding blocks (e.g., functional units) in conventional HLS techniques are assumed to have fixed latency values. Variable-latency units exhibit the pr operty that the number of cycles taken to compute their outputs varies depe nding on the input values. While variable-latency units offer potential for performance improvement, we demonstrate that realization of this potential requires that HLS be adapted suitably (sub-optimal use of variable-latency units can lead to performance degradation, or unnecessarily high area over heads). Our techniques to incorporate variable-latency units into HLS ensure that t he performance improvement is maximized, while minimizing area overheads or satisfying resource constraints. These techniques are not restricted to sp ecific HLS tools/algorithms, and can be plugged in to any generic HLS syste m. Since area overheads may still be incurred due to the use of variable-la tency units, we present a novel technique, based on the concept of reduced variable-latency units, to further reduce area overheads. Reduced variable- latency units only implement the low-latency case behavior of complete vari able-latency units. We demonstrate that the use of reduced variable-latency units significantly reduces area overheads, and sometimes results in impro vements in performance while simultaneously reducing the area of the regist er transfer level implementation. Experimental results show that the proposed variable-latency-unit-based syn thesis techniques achieve a performance improvement of upto 1.6X (average o f 1.4X) over a state-of-the-art HLS tool, with minimal area overheads (aver age of 5.3%). The use of reduced variable-latency units leads to a performa nce improvement of upto 1.6X (average of 1.3X), with a simultaneous area re duction of upto 17.9% (10.6% on the average).