Trench formation and filling technique for dielectric isolation of plasma display panel driver integrated circuits

Trench etching and filling technique for the isolation between the control (low voltage) and the power (high voltage) region in power integrated circu its was investigated. This technique consists of a deep trench formation (8 .0 mum) with positive etching using 45% He-O-2 of the HBr and SiF4 chemistr ies followed by filling and global planarization with the chemical mechanic al polishing technique. The novel trench etching technique provides better surface quality of 3.1 Angstrom roughness measured with atomic force micros copy. The filling and global planarization results in lower leakage current less than 1 nA at the supplying voltage of 400 V. (C) 2000 American Vacuum Society. [S0734-211X(00)03405-3].