A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation

Authors
Huang, YM Kuo, JB
Citation
Ym. Huang et Jb. Kuo, A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation, IEEE CIR-II, 47(10), 2000, pp. 1074-1079
Citations number
9
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
ISSN journal
10577130 → ACNP
Volume
47
Issue
10
Year of publication
2000
Pages
1074 - 1079
Database
ISI
SICI code
1057-7130(200010)47:10<1074:AHCCS(>2.0.ZU;2-5
Abstract
This paper reports a conditional tarry select (CCS) adder circuit with a su ccessively-incremented-carry-number block (SICNB) structure for law-voltage VLSI implementation, Owing to the successively-incremented-carry-number bl ock (SICNB) structure, the ne ir 16-bit SICNB CCS adder provides a 37% fast er speed as compared to the conventional conditional carry select adder bas ed on the SPICE results.