Design of the lower error fixed-width multiplier and its application

This brief develops a general methodology for designing a lower-error two's -complement fixed-width multiplier that receives two n-bit numbers and prod uces an n-bit product, By properly choosing the generalized index, we deriv e the better error-compensation bias to reduce the truncation error and the n construct a lower error fixed-width multiplier, which is area efficient f or VLSI implementation. Finally, we successfully apply the proposed fixed-w idth multiplier to realizing a digital FIR filter, which has shown that the performance is better than that using other fixed-width multipliers.