Sequential fault modeling and test pattern generation for CMOS iterative logic arrays

Iterative Logic Arrays (ILAs) are widely used in the datapath parts of digi tal circuits, like general purpose microprocessors, embedded processors, an d digital signal processors. Testing strategies based on more comprehensive fault models than the traditional combinational fault models have become a n imperative need in CMOS technology. In this paper, first, we introduce a comprehensive, cell-level, sequential fault model suitable for ILAs, termed Realistic Sequential Cell Fault Model (RS-CFM). RS-CFM drastically reduces test complexity compared to exhaustive two-pattern testing proposed so far in the literature for sequential ILA testing, without sacrificing test qua lity. In addition; it favors robustness of sequential test sets both at the cell and the array levels. Second, a new Automatic Test Pattern Generator (ILA-ATPG) based on RS-CFM for the case of one-dimensional ILAs is presente d. ILA-ATPG can handle all classes of one-dimensional ILAs: unilateral or b ilateral ILAs, with or without vertical inputs/outputs. Based on a graph mo del, ILA-ATPG explores the C-testability and linear-testability of the ILA under test and resolves the test invalidation problem constructing robust t est sequences. The efficiency of ILA-ATPG is demonstrated through a compreh ensive set of experimental results over all classes of one-dimensional ILAs , including ail practical one-dimensional ILAs, as well as a number of more complex benchmarks.