Performance analysis of hybrid network multiprocessor architecture

Citation
A. Averbuch et al., Performance analysis of hybrid network multiprocessor architecture, CONCURRENCY, 12(9), 2000, pp. 821-844
Citations number
11
Categorie Soggetti
Computer Science & Engineering
Journal title
CONCURRENCY-PRACTICE AND EXPERIENCE
ISSN journal
10403108 → ACNP
Volume
12
Issue
9
Year of publication
2000
Pages
821 - 844
Database
ISI
SICI code
1040-3108(20000810)12:9<821:PAOHNM>2.0.ZU;2-Q
Abstract
In this paper we investigate architectures that combine message-passing and shared-memory technologies, called hereinafter hybrid architectures, We in troduced hybrid architectures in which large buses of the shared-memory are split into a number of small high-performance shared-memory blocks, which are connected via message-passing architecture, such as hypercube, grid or ring. This way we avoid the possible degradation of the achieved performanc e due to the fact that the bus performance does not scale well when the num ber of processors it connects increases. We study the saturation situations of several hybrid network architectures, where adding processors does not reduce the overall execution time. We sho w that the use of hybrid network architectures leads to significant improve ment of the systems price/performance ratio, by significantly improving the performance with almost no system cost increment, Therefore, the usage of hybrid architectures demonstrates how minimal 'cost' spending could signifi cantly increase the system performance. In addition, we show that different types of applications have different best hybrid architectures, Copyright (C) 2000 John Wiley & Sons, Ltd.