Survey of architectures and performance of ATM switches based on deflection routing

ATM switch architectures based on deflection routing are here examined, des cribed in terms of a general switch model and compared with regards to thei r internal operations. Their common feature is the availability of multiple I/O paths through a multistage unbuffered interconnection network where co nflicts for the same interstage link are dealt with by deflecting packets o nto the wrong path. The main engineering parameter of the architecture, tha t is the number of network stages that provides a given packet loss perform ance is studied in depth. In particular it is found that basically all the examined architectures have a complexity on the order of N log(2) N in the range of switch size of usual interest. Furthermore it has been possible to rank the architectures with comparable complexity based on the loss perfor mance they provide. The Shuffleout switch turns out to behave better than o ther architectures previously known as providing an optimal performance.