This paper presents a novel flash memory cell based on localized charge tra
pping in a dielectric layer and on a new read operation. It is based on the
storage of a nominal similar to 400 electrons above a n(+)/p junction. Pro
gramming is performed by channel hot electron injection and erase by tunnel
ing enhanced hot hole injection, The new read methodology is very sensitive
to the location of trapped charge above the source, This single device cel
l has a two physical bit storage capability, The cell shows improved erase
performances, no over erase and erratic bit issues, very good retention at
250 degreesC, and endurance up to 1M cycles. Only four masks are added to a
standard CMOS process to implement a virtual ground array. In a typical 0.
35 mum process, the area of a bit is 0.315 mum(2) and 0.188 mum(2) in 0.25
mum technology. All these features and the small cell size compared to any
other flash cell make this device a very attractive solution for all NVM ap
plications.