Analysis of lateral DMOS power devices under ESD stress conditions

Authors
Mergens, MPJ Wilkening, W Mettler, S Wolf, H Stricker, A Fichtner, W
Citation
Mpj. Mergens et al., Analysis of lateral DMOS power devices under ESD stress conditions, IEEE DEVICE, 47(11), 2000, pp. 2128-2137
Citations number
23
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
47
Issue
11
Year of publication
2000
Pages
2128 - 2137
Database
ISI
SICI code
0018-9383(200011)47:11<2128:AOLDPD>2.0.ZU;2-L
Abstract
The physical mechanisms specific for 40V-LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission l ine pulse (TLP) measurements, human body model (HBM) testing, emission micr oscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. In homogeneous triggering caused by device topology as well as the sustained n onhomogeneous current flow due to the unusual electrical behavior are accur ately analyzed in single- and multi-finger devices.