A novel CMOS device architecture called silicon on nothing (SON) is propose
d, which allows extremely thin (in the order of a few nanometers) buried di
electrics and silicon films to be fabricated with high resolution and unifo
rmity guarantied by epitaxial process. The SON process allows the buried di
electric (which may be an oxide but also an air gap) to be fabricated local
ly in dedicated parts of the chip, which may present advantages in terms of
cost and facility of system-on-chip integration. The SON stack itself is p
hysically confined to the under-gate-plus-spacer area of a device, thus ena
bling extremely shallow and highly doped extensions, while leaving the HDD
(highly doped drain) junctions comfortably deep. Therefore, SON embodies th
e ideal device architecture taking the best elements from both bulk and SOI
and getting rid of their drawbacks. According to simulation results, SON e
nables excellent Ion/Ioff trade-off, suppressed self-heating, low SID serie
s resistance, close to ideal subthreshold slope, and high immunity to SCE a
nd DIBL down to ultimate device dimensions of 30 to 50 nm.