Silicon-on-nothing (SON) - an innovative process for advanced CMOS

Citation
M. Jurczak et al., Silicon-on-nothing (SON) - an innovative process for advanced CMOS, IEEE DEVICE, 47(11), 2000, pp. 2179-2187
Citations number
38
Categorie Soggetti
Eletrical & Eletronics Engineeing
Journal title
IEEE TRANSACTIONS ON ELECTRON DEVICES
ISSN journal
00189383 → ACNP
Volume
47
Issue
11
Year of publication
2000
Pages
2179 - 2187
Database
ISI
SICI code
0018-9383(200011)47:11<2179:S(-AIP>2.0.ZU;2-R
Abstract
A novel CMOS device architecture called silicon on nothing (SON) is propose d, which allows extremely thin (in the order of a few nanometers) buried di electrics and silicon films to be fabricated with high resolution and unifo rmity guarantied by epitaxial process. The SON process allows the buried di electric (which may be an oxide but also an air gap) to be fabricated local ly in dedicated parts of the chip, which may present advantages in terms of cost and facility of system-on-chip integration. The SON stack itself is p hysically confined to the under-gate-plus-spacer area of a device, thus ena bling extremely shallow and highly doped extensions, while leaving the HDD (highly doped drain) junctions comfortably deep. Therefore, SON embodies th e ideal device architecture taking the best elements from both bulk and SOI and getting rid of their drawbacks. According to simulation results, SON e nables excellent Ion/Ioff trade-off, suppressed self-heating, low SID serie s resistance, close to ideal subthreshold slope, and high immunity to SCE a nd DIBL down to ultimate device dimensions of 30 to 50 nm.