A novel adiabatic register file design

A novel 8-word x 16-bit adiabatic register file is designed. The adiabatic circuits are based on the Pass-transistor Adiabatic Logic with NMOS pull-do wn configuration (PAL-2N). Using adiabatic switching technique, the power c onsumption of the register file is significantly reduced as the energy tran sferred to the large capacitance buses is mostly recovered. HSPICE simulati on results have shown power savings of more than 77% as compared to the con ventional CMOS implementation. Although the proposed register file is desig ned with only one read port and one write port, multiple read and/or write ports can be easily constructed by adding additional read and/or write port transistors.