An analytical model of the temperature distribution in integrated circuits
is presented. The solution is based on a classic method of electrostatics:
the integration of the temperature field produced by a point source. Using
this approach, the temperature distribution is expressed by a closed-form a
nalytical relation, while previous approaches involve the summation of a sl
owly convergent series (Fourier series method) or a numerical integration p
rocedure (Fourier transform method). Therefore, the present approach is muc
h more computationally effective, and is particularly suitable for being in
corporated into electro-thermal simulation codes. Another significant advan
tage of the proposed analytical formulation is that a more clear understand
ing of the influence of geometric and layout parameters on the thermal beha
vior can be gained.
The analysis applies to arbitrarily located surface or volume heat sources.
Boundary conditions are properly taken into account using the method of im
ages. Finally, an accurate analytical expression for the thermal resistance
of an integrated device is derived, which accounts for all relevant geomet
ric parameters. This result may be a useful guideline in the early stages o
f layout optimization. (C) 2000 Elsevier Science Ltd. All rights reserved.