Tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits

A new test architecture, called TLS (tree-LFSR/SR), generates pseudo-exhaus tive test patterns for both combinational and sequential VLSI circuit is pr esented. Instead of using a single scan chain, the proposed test architectu re routes a scan tree driven by the LFSR to generate all possible input pat terns for each output cone. The new test architecture is able to take advan tages of both signal sharing and signal reuse. The benefits are: the diffic ulty of test architecture synthesis can be eased by accelerating the search ing process of appropriate residues; and the number of XOR gates to satisfy the pseudo-exhaustive test criterion can be reduced. The TLS test scheme m ainly contains three phases: backbone generation, tree growing, and XOR-tre e generation. Experimental results obtained by simulating combinational and sequential benchmark circuits are very encouraging.