The first IA-64 microprocessor

The first implementation of the IA-64 architecture achieves high performanc e by using a highly parallel execution core, while maintaining binary compa tibility with the IA-32 instruction set, Explicitly parallel instruction co mputing (EPIC) design maximizes performance through hardware and software s ynergy, The processor contains 25.4 million transistors and operates at 800 MHz. The chip is fabricated in a 0.18-mum CMOS process with six metal laye rs and packaged in a 1012-pad organic land grid array using C4 (flip-chip) assembly technology. A core speed back-side bus connects the processor to a 4-MB L3 cache.