Clock generation and distribution for the first IA-64 microprocessor

The clock design for the first implementation of the IA-64 microprocessor i s presented, A clock distribution,vith an active distributed deskewing tech nique is used to achieve a low skew of 28 ps, This technique is capable of compensating skews caused by within-die process variations that are becomin g a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providi ng support for intentional clock skew injection and time borrowing, By prov iding test access port interface to the deskew architecture and the incorpo ration of the on-die-clock-shrink, this design is equipped with two very po werful post-silicon timing debug tools that are critical to high-performanc e microprocessor design and enabled quick time-to-market.